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IEEE-Std. 1149.6 compliant JTAG/Boundary Scan I/O module

Boundary Scan Products
IEEE-Std. 1149.6 compliant JTAG/Boundary Scan I/O module

IEEE-Std. 1149.6 compliant JTAG/Boundary Scan I/O module
The I/O module called CION Module/FXT114S from Goepel electronic is controlled via a standard Test Access Port (TAP) and provides a total of 114 parallel I/O channels with IEEE-Std. 1149.1 compliant test resources, where 50 of those channels also support IEEE-Std. 1149.6 for the structural test of high-speed differential interfaces. Due to its small dimensions, the module can easily be integrated into test adapters. “With this new I/O module we are addressing the growing demand for structural test support of Advanced Digital Network featuring IEEE 1149.6 capabilities”, says Raj Puri, Vice President Marketing and Sales at Goepel electronics.

The module provides 64 single-ended test channels, controlled by CION ASIC devices. All channels are independently controllable as Input/Output/Tristate and the I/O voltage can be programmed from 1.8 V to 5.0 V in groups of 32 channels. Additional pin driver features support a high current capability, while special safety measures, such as the ‚unstress’ feature, protect the UUT against damage in case of shorts. In addition the module provides 50 differential (LVDS) channels with IEEE 1149.1 and IEEE 1149.6 compliant test resources. Of those differential channels, 25 are configured as inputs and the other 25 are configured as outputs. Multiple CION modules of the same or different types are easily daisy-chained through their TAP interfaces. These capabilities make the module suitable for the test of non-scannable circuit clusters, peripheral connectors, backplanes, and AC-coupled networks in many applications. The module is fully supported in the integrated JTAG/Boundary Scan software platform System Cascon and can be used with any ScanBooster and Scanflex Boundary Scan controller. The user can easily include the module in a test project, generate the desired test vectors fully automated. Detected faults are visualized at pin and net-level and the UUT is debugged interactively.
SMT, booth 7-318, 7-404
NEW UK, E 30
EPP Europe 463
Current Issue
Titelbild EPP EUROPE Electronics Production and Test 11
Issue
11.2023
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